1. Datasheet 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Intel® Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Intel® Stratix® 10 and Intel® Arria® 10 IP Variants B. Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Intel® Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
The Ethernet Toolkit offers the following features when used with hardware design that has standalone Ethernet IP as well as with an Intel® Quartus® Prime generated Ethernet IP design example:
- Verifies the status of the Ethernet link.
- Reads and writes to status and configuration registers of the IP.
- Displays the values of TX/RX status and statistics registers.
- Ability to assert and deassert IP resets.
- Verifies the IPs error correction capability.
The Ethernet Toolkit also offers some additional features when used with an Intel® Quartus® Prime generated Ethernet IP design example:
- Provides access to the example design packet generator.
- Execute testing procedures to verify the functionality of Ethernet IPs.
- Enable and disable MAC loopback.
- Set source and destination MAC addresses.
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