Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Document Table of Contents

6.5. Transceiver Reconfiguration Signals

You access the transceiver control and status registers using the transceiver reconfiguration interface. This is an Avalon® -MM interface.

The Avalon® -MM interface implements a standard memory-mapped protocol. You can connect an Avalon master to this bus to access the registers of the embedded Transceiver PHY IP core.

Table 17.  Reconfiguration Interface Ports with Shared Native PHY Reconfiguration InterfaceThese signals are synchronous to mgmt_clk.
Signal Name Direction Description
reconfig_write Input Write enable signal. Signal is active high.
reconfig_read Input Read enable signal. Signal is active high.
reconfig_address[10:0] Input Address bus. The lower 10 bits specify address and the upper bit specifies the channel (bit [10] is always 0) .
reconfig_writedata[31:0] Input A 32-bit data write bus. reconfig_address specifies the address.
reconfig_readdata[31:0] Output A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted.
reconfig_waitrequest Output Indicates the Avalon® -MM interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted.