Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Document Table of Contents

7.1.2. Hardware Design Example Components

Figure 11.  Intel® Stratix® 10 10GBASE-KR PHY Hardware Design Example High Level Block Diagram
The Intel® Stratix® 10 10GBASE-KR hardware design example includes the following components:
  1. 10GBASE-KR PHY IP core.
  2. ATX PLL to generate the high-speed serial clock to drive the device transceiver channel.
  3. fPLL to generate XGMII clock.
  4. IO-PLL to generate a 125 MHz clock from the 50 MHz oscillator.
  5. Packet Generator and Packet Checker.
  6. JTAG controller that communicates with System Console. You communicate with the client logic through the System Console.
    Table 19.   Intel® Stratix® 10 10GBASE-KR PHY IP Core Hardware Design Example File Descriptions

    File Names


    de_wrapper.qpf Intel® Quartus® Prime project file
    de_wrapper.qsf Intel® Quartus® Prime project settings file
    de_wrapper.sdc, de_wrapper_clk.sdc Synopsys Design Constraints file. You can copy and modify this file for your own design

    Main file for accessing System Console