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1. Datasheet
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Intel® Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Intel® Stratix® 10 and Intel® Arria® 10 IP Variants
B. Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide
7.1.1. Design Example Directory Structure
7.1.2. Hardware Design Example Components
7.1.3. Simulation Design Example Components
7.1.4. Generating the Design Example
7.1.5. Simulating the Intel® Stratix® 10 10GBASE-KR Design Example Testbench
7.1.6. Compiling and Configuring the Design Example in Hardware
7.1.7. Testing the Hardware Design Example
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7.1.2. Hardware Design Example Components
Figure 11. Intel® Stratix® 10 10GBASE-KR PHY Hardware Design Example High Level Block Diagram
The Intel® Stratix® 10 10GBASE-KR hardware design example includes the following components:
- 10GBASE-KR PHY IP core.
- ATX PLL to generate the high-speed serial clock to drive the device transceiver channel.
- fPLL to generate XGMII clock.
- IO-PLL to generate a 125 MHz clock from the 50 MHz oscillator.
- Packet Generator and Packet Checker.
- JTAG controller that communicates with System Console. You communicate with the client logic through the System Console.
Table 19. Intel® Stratix® 10 10GBASE-KR PHY IP Core Hardware Design Example File Descriptions File Names
Description
de_wrapper.qpf Intel® Quartus® Prime project file de_wrapper.qsf Intel® Quartus® Prime project settings file de_wrapper.sdc, de_wrapper_clk.sdc Synopsys Design Constraints file. You can copy and modify this file for your own design console.tcl Main file for accessing System Console
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