Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
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7.1.3. Simulation Design Example Components

The simulation design example top-level test file is testbench.v.
Table 20.   Intel® Stratix® 10 10GBASE-KR PHY IP Core Testbench File Descriptions
File Name Description
Testbench and Simulation Files
testbench.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
run_vsim.do The Mentor Graphics ModelSim* script to run the testbench.
run_vcs.sh The Synopsys VCS* script to run the testbench.
run_ncsim.sh The Cadence NCSim* script to run the testbench.

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