Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
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2.5.2. Adding the Transceiver PLL

Intel® Stratix® 10 10GBASE-KR PHY IP core requires an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with other transceivers in your design.

The TX transceiver PLL is instantiated with an Intel FPGA ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the Intel® Stratix® 10 10GBASE-KR PHY IP core.

You can use the IP Catalog to create a transceiver PLL.
  • Select Stratix 10 L-Tile/H-Tile Transceiver ATX PLL.
  • In the parameter editor, set the following parameter values:
    • PLL output frequency to 5156.25 MHz
    • PLL auto mode reference clock frequency (integer) to 644.53125 MHz or 322.265625 MHz

You must connect the tx_serial_clk input pin of the Intel® Stratix® 10 10GBASE-KR IP core PHY link to the output port of the ATX PLL.

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