Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Public
Document Table of Contents

1.1. Intel® Stratix® 10 10GBASE-KR PHY IP Core Supported Features

The Intel® Stratix® 10 10GBASE-KR PHY IP core supports the following features:
  • Auto-negotiation (AN) for backplane Ethernet as defined in Clause 73 of the IEEE 802.3 2015 Standard.
  • 10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the IEEE 802.3 2015 Standard. In addition to the link-partner TX tuning as defined in Clause 72, this PHY also automatically configures the local device RX interface to achieve less than 10-12 bit error rate (BER) target.
  • Forward error correction (FEC) as defined in Clause 74 of the IEEE 802.3 2015 Standard. This is an optional feature which provides an error detection and correction mechanism.
  • The Intel® Stratix® 10 10GBASE-KR PHY IP core includes the following modules to enable operation over a backplane:
    • Auto-negotiation (AN)— The 10GBASE-KR PHY IP core can auto-negotiate between 10GBASE-KR, and 10GBASE-KR with FEC PHY types. The AN function is mandatory for Backplane Ethernet.
    • Link training (LT)— The LT mechanism allows the 10GBASE-KR PHY to automatically configure the link-partner TX PMDs for the lowest Bit Error Rate (BER).

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