Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Public
Document Table of Contents

C. Document Revision History for Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.01.29 20.1 19.1.0 Added Ethernet toolkit debugging tool description in the Supported Tools chapter.
2019.07.19 19.2 19.1.1
  • Intel® Stratix® 10 L-tile device support is now available for this IP in the current of the Intel® Quartus® Prime software.
  • Renamed the parameter Altera Debug Master Endpoint to Native PHY Debug Master Endpoint.
  • Added the following new parameters:
    • VCCR_GXB and VCCT_GXB supply voltage for the transceiver
    • Enable JTAG to Avalon Master Bridge
  • Modified the following commands in section Testing the Hardware Design Example:
    • reg_read to reconfig_read
    • reg_write to reconfig_write
2019.04.30 17.1 17.1
  • Clarified the supported core speed grade in section IP Core Speed Grade Support.
  • Made the following changes in Table: Test Harness Register Map:
    • Modified registers names:
      • XGMII rx_ready to rx_data_ready
      • XGMII test_done to test_done
    • Updated the description of the signals: rx_data_ready, XGMII_checker_pass, rx_mismatch, XGMII fifo_full, XGMII test_done, and XGMII frame_done.
    • Added new register XGMII RX frame_count channel 0
Date Version Changes
November 2017 2017.11.06
  • Updated for Intel® Quartus® Prime Pro Edition 17.1 release.
  • Added new chapter Getting Started explaining how to install, generate and integrate IP core in your design.
  • Added new chapter Design Example to demonstrate the functions of the IP core.
  • Updated device support for Intel® Stratix® 10 device with L-Tile transceivers in Table: Intel® Stratix® 10 10GBASE-KR PHY IP Core Device Family Support.
  • Changed chapter title from About Intel® Stratix® 10 10GBASE-KR PHY IP Core to Datasheet.
  • Modified chapter Datasheet to document the Intel® Stratix® 10 10GBASE-KR PHY IP Core Supported Features.
  • Updated description of Target Stratix-10 transceiver tile, Avalon® -MM clock frequency, and Link fail inhibit time for 10Gb Ethernet parameters in Table: Intel® Stratix® 10 10GBASE-KR PHY IP Core Parameters: IP Tab.
  • Added bits 2, 3, 18, 19, [22:20], [27:23], [31:38] to register address 0x4D0.
  • Corrected encoding for 1000BASE-KX and 10GBASE-KX4 mode of KR AN Link Ready [5:0] register.
  • Changed the register address 0x4B0 [8] to reserved.
  • Updated description of Tab PMA parameters in Table: Intel® Stratix® 10 10GBASE-KR PHY IP Core Parameters: IP Tab.
  • Corrected description of lcl_rf signal in Control and Status Signals section.
  • Removed signal reconfig_reset from Transceiver Reconfiguration Signals section.
  • Added new clock signal rx_div_clk in Clock and Reset Signals section.
  • Added VHDL simulation model support.
June 2017 2017.06.08 Initial release.

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