Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Public
Document Table of Contents

6.6. Control and Status Signals

Table 18.  Control and Status Signals
Signal Name Direction Clock Domain Description
rx_block_lock Output Synchronous to rx_clkout When asserted, indicates the block synchronizer has established synchronization.
rx_hi_ber Output Synchronous to rx_clkout When asserted, indicates the BER monitor block detects a a Sync Header high bit error rate greater than 10-4.
rx_is_lockedtodata Output Asynchronous signal When asserted, indicates the RX channel is locked to input data.
tx_cal_busy Output Synchronous to mgmt_clk When asserted, indicates that the TX channel is being calibrated.
rx_cal_busy Output Synchronous to mgmt_clk When asserted, indicates that the RX channel is being calibrated.
lcl_rf Input Synchronous to xgmii_tx_clk When asserted, indicates a Remote Fault (RF).The MAC sends this fault signal to its link partner. This corresponds to bit D13 of the Auto Negotiation Link Codeword Base Page.
rx_data_ready Output Synchronous to xgmii_rx_clk When asserted, indicates that the MAC can begin sending data to the PHY.
pcs_mode_rc [5:0] Output Synchronous to mgmt_clk Specifies the PCS mode for reconfiguration. One-hot encoded. This signal has the following valid values:
  • 6'b000001: Auto-Negotiation mode
  • 6'b000010: Link Training mode
  • 6'b000100: 10GBASE-KR data mode
  • 6'b001000: Reserved
  • 6'b010000: Reserved
  • 6'b100000:10G data mode with FEC

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