Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Public
Document Table of Contents

2.5.3. Adding the fPLL

Intel® Stratix® 10 cores require an external fPLL to drive the xgmii_tx_clk and xgmii_rx_clk clock signals. You can use single fPLL across multiple instances of 10GBASE-KR PHY IP core.

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