Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
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7.2.4. Intel® Stratix® 10 10GBASE-KR PHY Design Example Registers

Table 23.   Intel® Stratix® 10 10GBASE-KR Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reconfig_read and reconfig_write functions in the System Console.

Word Offset

Name

Description

0x0000–0x07FF

CH0_PHY Channel 0 Native PHY access

0x0800–0x08FF

CH0_PHY Channel 0 10G-Base-KR IP CSR access
0x1000–0x17ff CH1_PHY Channel 1 Native PHY access
0x1800–0x18FF CH1_PHY Channel 1 10G-Base-KR IP CSR access
0xF000–0xFFFF Test Harness Refer to the table Test Harness Register Map
Note: For an example, to access 0x4B0 address of CH0 IP register, use the absolute address 0x4B0+0x800 that is 0xCB0.
Table 24.   Test Harness Register Map

Word Offset

Bit R/W Name

Description

0x00

0 RWSC Start XGMII packets When set to 1, sends the specified number of XGMII packets.

0x01

0 RW Reset Hold When set to 1, holds the channel in reset. This bit must be written to 0 for normal operation.
8 RW Generator Reset When set to 1, holds the XGMII and GMII generators in reset. Bit must be written to 0 for normal operation.

0x02

0 R rx_data_ready When asserted, indicates the block synchronizer has successfully established synchronization. The incoming XGMII data block locks the receiver.
1 R XGMII checker_pass When asserted indicates that the received frames are exactly same as the transmitted frames. When XGMII rx_mismatch asserted, this is set to 0.
2 R XGMII rx_mismatch Asserted even if single received frame doesn't match the transmitted frame.
3 R XGMII fifo_full Shows the XGMII FIFO on the TX side is full. When set to 1, indicates error condition.
4 R test_done When asserted indicates that the transmitter sent all 418 frames. Each frame is 64-bit wide data and 2-bit control.
5 R XGMII frame_done When asserted indicates that the transmitter finished sending particular type of frames and then goes low automatically.
6 R XGMII test_pass When asserted, XGMII has received all sent packets and there is no mismatch in received data.

XGMII status= rx_data_ready & checker_pass & ! rx_mismatch

0x03

Reserved
0x04 [31:0] RSC XGMII RX frame_count channel 0 Non-idle frame count on the RX side of channel 0. This is self clearing on read.
0x05–0xFF Reserved

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