4. Functional Description
The Intel FPGA 10GBASE-KR PHY IP core implements an Ethernet MAC in accordance with the 802.3 2015 Standard. The IP core implements an Ethernet PCS and PMA (PHY) that handles the frame encapsulation and flow of data between a client logic and Ethernet network. The following figure shows the supporting components inside the Intel® Stratix® 10 10GBASE-KR PHY IP core.
The Intel® Stratix® 10 10GBASE-KR PHY IP core includes the following components:
Enhanced PCS Datapaths
The Enhanced PCS and PMA inside the Native PHY are configured as a 10GBASE-R PHY. Refer to the PCS architecture chapters of Intel® Stratix® 10 Transceiver PHY User Guide for more details on how these blocks support 10G protocols and FEC.
Auto Negotiation, IEEE 802.3 Clause 73
The auto-negotiation component synchronizes the start time of the link training on both sides of the link. This function ensures that the link training can complete in 500 ms or less, as required by the IEEE specification.
Link Training (LT), IEEE 802.3 Clause 72
Intel® Stratix® 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72 standard training procedure. This IP includes:
- Training frame lock that is different from the regular 64b/66b frame_lock
- Training frame generation
- The control channel codec
- Local Device (LD) coefficient update
- Link Partner (LP) coefficient generation
The Reconfiguration Block performs Avalon® Memory-Mapped Interface ( Avalon® -MM) writes to the PHY for both PCS and PMA reconfiguration. The Avalon® -MM master accepts requests from the PMA or PCS controller. It performs Read-Modify-Write or Write commands on the Avalon® -MM interface. The PCS controller receives rate change requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and PCS.
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