You can simulate your Intel® Stratix® 10 10GBASE-KR IP core variation with the functional simulation model and the testbench generated with the design example provided with this IP core. The functional simulation model is a cycle-accurate model that allows for fast functional simulation of your IP core instance using industry-standard Verilog or VHDL simulators. For more information, refer to Design Example section.
The functional simulation model and testbench files are generated in project subdirectories. These directories also include scripts to compile and run the design example.