Intel® Stratix® 10 10GBASE-KR PHY IP Core User Guide

ID 683500
Date 1/29/2021
Public
Document Table of Contents

6.4. Avalon® -MM Interface Signals

Table 16.  Avalon-MM Interface SignalsThe Avalon-MM slave interface signals provide access to all registers.
Signal Name Direction Clock Domain Description
mgmt_clk Input Clock The clock signal that controls the Avalon-MM PHY management interface.

This clock is used for both the PHY management interface and transceiver reconfiguration. You must restrict the frequency to a rate between 100 MHz and 161 MHz (inclusive) to meet the specification for the transceiver reconfiguration clock.

mgmt_clk_reset Input Asynchronous reset Resets the PHY management interface. This asynchronous signal is active high and level sensitive.
mgmt_addr[10:0] Input Synchronous to mgmt_clk 11-bit Avalon-MM address.
mgmt_writedata[31:0] Input Synchronous to mgmt_clk Input data.
mgmt_readdata[31:0] Output Synchronous to mgmt_clk Output data.
mgmt_write Input Synchronous to mgmt_clk Write signal. Active high.
mgmt_read Input Synchronous to mgmt_clk Read signal. Active high.
mgmt_waitrequest Output Synchronous to mgmt_clk When asserted, indicates that the Avalon-MM slave interface is unable to respond to a read or write request. When asserted, control signals to the Avalon-MM slave interface must remain constant.

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