In a typical design flow, the early stages of development concentrate
on meeting timing, area and power goals. Once the design meets those goals, the efforts
focus on improving performance. This chapter introduces techniques
and tools in the
Quartus® Prime software that you can use
to achieve the highest design performance.
Optimization of a FPGA design requires a multi-dimensional approach that meets the design goals
while reducing area, critical path delay, power consumption, and runtime. The
Quartus® Prime software includes advisors to address each of
these issues. By implementing the advisor's suggestions, you can reduce the time spent
on design iterations.
Intel® FPGAs have a unique timing model that contains delay
information for all physical elements in the device, such as combinational adaptive logic
modules, memory blocks, interconnects, and registers.
The delays encompass all
valid combinations of operating conditions for the target FPGA. Additionally, the device size
and package determine pin-out and the resource availability.
can vary significantly depending on the assignments and settings that you choose. In the
Quartus® Prime software, the default values for settings
and options provide the best trade-off between compilation time, resource utilization, and
Before compiling a design in the
Quartus® Prime software, consider the following guidelines.
Guidelines for I/O Assignments
In a FPGA design, I/O standards and
drive strengths affect I/O timing.
When specifying I/O assignments, make sure that the
Quartus® Prime software is using an accurate I/O timing delay for timing
analysis and Fitter optimizations.
If the PCB layout does not indicate pin locations, then leave the pin locations
unconstrained. This technique allows the Compiler to search for the best layout.
Otherwise, make pin assignments to constrain the compilation appropriately.
For best results, use real time requirements. Applying more demanding timing
requirements than the design needs can cause the Compiler to trade off by increasing
resource usage, power utilization, or compilation time.
Comprehensive timing requirement settings
achieve the best results for the following reasons:
Correct timing assignments enable the software to work
hardest to optimize the performance of the timing-critical parts of the design
and make trade-offs for performance. This optimization can also save area or
power utilization in non-critical parts of the design.
If enabled, the
Quartus® Prime software performs physical synthesis optimizations based
on timing requirements.
Quartus® Prime Timing Analyzer determines if the design implementation meets
the timing requirement. The Compilation Report shows whether the design meets the
timing requirements, while the timing analysis reporting commands provide detailed
information about the timing paths.
Many optimization goals can conflict
with one another, so you might need to resolve conflicting goals.
Table 1. Examples of Trade offs in Design Optimization
Resource usage and critical path timing.
Certain techniques (such as logic duplication) can improve timing
performance at the cost of increased area.
Power requirements can result in area and timing
For example, reducing the number of available high-speed tiles,
or attempting to shorten high-power nets at the expense of critical
System cost and time-to-market considerations can affect the
choice of device.
For example, a device with a higher speed grade or more clock
networks can facilitate timing closure at the expense of higher
power consumption and system cost.
Finally, constrains that are too severe limit design
feasibility as far as no possible solution for the selected device. If the Fitter
cannot resolve a design due to resource limitations, timing constraints, or power
constraints, consider rewriting parts of the HDL code.
By default, the
Quartus® Prime Fitter
might physically spread a design over the entire device to meet the set timing
If you prefer to optimize your design to use the smallest area,
you can change this behavior. If you require reduced area, you can enable
certain physical synthesis options to modify your netlist to create a more
area-efficient implementation, but at the cost of increased runtime and
To meet complex timing requirements involving
multiple clocks, routing resources, and area constraints, the
Quartus® Prime software offers a close interaction between synthesis, floorplan
editing, place-and-route, and timing analysis processes.
By default, the
Quartus® Prime Fitter works to meet the timing requirements, and
stops when the requirements are met. Therefore, realistic constraints are
crucial for timing closure.
Under-constrained designs can lead to
sub-optimal results. For over-constrained designs, the Fitter might
over-optimize non-critical paths at the expense of true critical paths. In
addition, area and compilation time may also increase.
For designs with high resource usage, the
Quartus® Prime Fitter might have trouble finding a
legal placement. In such circumstances, the Fitter automatically modifies
settings to try to trade off performance for area.
Quartus® Prime Fitter
offers advanced options that can help improve the design performance when
you properly set constraints. Use the Timing Optimization Advisor to
determine which options are best suited for the design.
In high-density FPGAs, routing accounts for a major part
of critical path timing. Because of this, duplicating or retiming logic can
allow the Fitter to reduce delay on critical paths. The
Quartus® Prime software offers push-button netlist
optimizations and physical synthesis options that can improve design
performance at the expense of considerable increases of compilation time and
area. Turn on only those options that help you keep reasonable compilation
times and resource usage. Alternately, you can modify the HDL to manually
duplicate or adjust the timing logic.
Many Fitter settings influence compilation time. Most of the default settings in the
Quartus® Prime software are set for reduced compilation time. You can modify these settings based on your project requirements.
Quartus® Prime software
supports parallel compilation in computers with multiple processors. This can reduce
compilation times by up to 15%.
Quartus® Prime software includes several advisors to help you optimize your
design and reduce compilation time.
The advisors provide recommendations based on the project settings and design constraints. Those recommendations can help you to fit the project, meet timing or power requirements, or improve the design performance.
The advisors organize the recommendations from general to specific. Where applicable, the categories are divided into of stages presented by complexity.
The Design Space Explorer II tool (DSE
II) provides an easy and efficient way for you to run experiments on your design
settings. You can run a single compilation locally on your PC or remotely using compute
The Design Space Explorer II tool
(Tools > Launch Design Space Explorer II) allows you to find optimal project settings for resource,
performance, or power optimization goals.Design Space Explorer II (DSE II) processes
a design using combinations of
and constraints, and reports the best settings for the design. You can take advantage of
the DSE II parallelization abilities to compile on multiple computers.
If a design is
close to meeting timing or area requirements, you can try different seeds with
the DSE II, and find one seed that meets timing or area requirements.
Figure 1. Design Space Explorer II
You can run DSE II at any step in the design process; however,
because large changes in a design can neutralize gains achieved from optimizing
Intel® FPGA recommends that
you run DSE II late in the design cycle.
In DSE II, an exploration point is a collection of
Analysis & Synthesis, Fitter, and placement settings, and a group of exploration points is
a design exploration. A design exploration can also include different
compiles the design using the settings corresponding to each exploration point.
When the compilation finishes, DSE II evaluates the performance data against
an optimization goal that you specify. You can direct the DSE II to optimize for
area, or power.
You can configure DSE II to take advantage of
your computing resources to run the design explorations.
In the DSE II GUI, the
Setup page contains the job launch options, and the
Status page allows you to monitor and control
DSE II supports running compilations on your
local computer or a remote host through LSF, SSH or Torque. For SSH,
can also define a comma-separated list of remote hosts.
If you have a laptop
or standard computer, you can use the single compilation feature to compile your design on a
workstation with higher computing performance and memory capacity.
When running on a compute farm, you can direct the DSE II
exit after submitting all the jobs while the compilations continue to run
until completion. Optionally, you can receive an e-mail when the compilations are
If you launch jobs using
the remote host must enable public and private key authentication.
encrypted with a pass phrase, the remote host must run the ssh key agent
to decrypt the private
key, so the
quartus_dse executable can access the
Note: Windows remote hosts require Cygwin's sshd
server and PuTTY.
DSE II provides a collection of predefined exploration spaces that focus on
what you want to optimize. Additionally, you can define a set of compilation seeds. The number
of explorations points is the number of seeds multiplied by the number of exploration
Note: The availability of predefined spaces
depends on the device family that the design targets.
In the DSE GUI, you specify these settings in the Exploration page.
DSE II compares the compilation results to determine the best
Quartus® Prime software settings for the design. The
Report page displays a summary of results.
In an exploration, DSE II selects the best worst-case slack value from
among all timing corners across all exploration points. If you want to optimize for
worst-case setup slack or hold slack, specify timing constraints in the
Quartus® Prime software.
By default, DSE II saves all the compilation data. You can save disk space
by limiting the type of files that you want to save after a compilation finishes. These
settings are in the Exploration page, Results
DSE II has reporting tools that help you quickly determine important design
metrics, such as worse-case slack, across all exploration points.
DSE II provides a performance data report for all points it explores and
saves the information in a project-name.dse.rpt file in the project directory. DSE II
archives the settings of the exploration points in
Quartus® Prime Archive Files (.qar).
Performing a Design Exploration with the DSE II Utility
Note: Before running DSE II, specify the timing
constraints for the design.
This description covers the type of settings that you need to define when you want to
run a design exploration. For details about all the options available in the GUI,
refer to the
Quartus® Prime Help.
To perform a design exploration with the DSE II tool:
Start the DSE II tool.
If you have an open project in the
Quartus® Prime software and
launch DSE II, a dialog box appears asking if you want to close the
Quartus® Prime software. Click Yes.
In the Project page, specify the project and revision
that you want to explore.
In the Setup page, specify whether you want to perform a local or a remote exploration, and set up the job launch.
In the Exploration page, specify optimization settings
The following revision history applies to this
Quartus® Prime Version
General topic reorganization.
how DSE II works, and the main steps to follow when
performing a design exploration.
Added mention to the Design Partition
Planner in Design Analysis topic.
Implemented Intel rebranding.
Removed statements about serial equivalence when
using multiple processors.
Changed instances of Quartus
II to Quartus Prime.
Updated location of Fitter Settings,
Analysis & Synthesis Settings, and Physical Synthesis
Optimizations to Compiler Settings.
Updated DSE II content.
Minor changes for
Added the information about
initial compilation requirements. This section was moved from the
Area Optimization chapter of the
Quartus® Prime Handbook. Minor updates to delineate division
of Timing and Area optimization chapters.
Removed survey link.
Changed to new document template.
No change to content.
Initial release. Chapter based on
topics and text in Section III of volume 2.
This chapter describes how you can use the
Quartus® Prime Netlist Viewers to analyze and debug your designs.
As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize, and constrain your design is
critical. With today’s advanced designs, several design engineers are involved in coding and synthesizing different design blocks, making it difficult to
analyze and debug the design. The
Quartus® Prime RTL Viewer and Technology Map Viewer provide powerful ways to view your
initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.
When to Use the Netlist Viewers: Analyzing Design Problems
You can use the Netlist Viewers to analyze and debug your design. The following simple examples show how to use the
RTL Viewer and Technology Map Viewer to analyze problems encountered in the design process.
Using the RTL Viewer is a good way to view your initial synthesis results to determine whether you have created the
necessary logic, and that the logic and connections have been interpreted correctly by the software. You can use the RTL Viewer to check your design
visually before simulation or other verification processes. Catching design errors at this early stage of the design process can save you valuable time.
If you see unexpected behavior during verification, use the RTL Viewer to trace through the netlist and ensure that
the connections and logic in your design are as expected. Viewing your design helps you find and analyze the source of design problems. If your design
looks correct in the RTL Viewer, you know to focus your analysis on later stages of the design process and investigate potential timing violations or
issues in the verification flow itself.
You can use the Technology Map Viewer to look at the results at the end of Analysis and Synthesis. If you have compiled your design
through the Fitter stage, you can view your post‑mapping netlist in the Technology Map Viewer (Post-Mapping) and your post‑fitting netlist in the
Technology Map Viewer. If you perform only Analysis and Synthesis, both the Netlist Viewers display the same post‑mapping netlist.
In addition, you can use the RTL Viewer or Technology Map Viewer to locate the source of a particular signal, which can help you debug
your design. Use the navigation techniques described in this chapter to search easily through your design. You can trace back from a point of interest
to find the source of the signal and ensure the connections are as expected.
The Technology Map Viewer can help you locate post‑synthesis nodes in your netlist and make assignments when optimizing your design.
This functionality is useful when making a multicycle clock timing assignment between two registers in your design. Start at an I/O port and trace
forward or backward through the design and through levels of hierarchy to find nodes of interest, or locate a specific register by visually inspecting
Throughout your FPGA design, debug, and optimization stages, you can use all of the netlist viewers in many ways to increase your
productivity while analyzing a design.
Intel Quartus Prime Design Flow with the Netlist Viewers
When you first open one of the Netlist Viewers after compiling
the design, a preprocessor stage runs automatically before the Netlist Viewer
Click the link in the preprocessor process box to go to the Settings > Compilation Process Settings page where you can turn on the Run Netlist Viewers
preprocessing during compilation option. If you turn this option on, the
preprocessing becomes part of the full project compilation flow and the Netlist Viewer opens
immediately without displaying the preprocessing dialog box.
Quartus® Prime Design Flow Including the RTL Viewer and Technology Map Viewer
This figure shows how Netlist Viewers fit into the basic
Quartus® Prime design flow.
Before the Netlist Viewer can run the preprocessor stage, you must compile your design:
To open the RTL Viewer first perform Analysis and Elaboration.
To open the Technology Map Viewer (Post-Fitting) or the Technology Map Viewer (Post‑Mapping),
first perform Analysis and Synthesis.
The Netlist Viewers display the results of the last successful compilation.
Therefore, if you make a design change that causes an error during Analysis and Elaboration, you cannot view the netlist for the new design files,
but you can still see the results from the last successfully compiled version of the design files.
If you receive an error during compilation and you have not yet successfully run the appropriate compilation stage for your project, the Netlist
Viewer cannot be displayed; in this case, the
Quartus® Prime software issues an error message when you try to open the
Note: If the Netlist Viewer is open when you start a new compilation, the Netlist Viewer closes
automatically. You must open the Netlist Viewer again to view the new design netlist after compilation completes successfully.
RTL Viewer Overview
The RTL Viewer allows you to view a register transfer level (RTL) graphical representation of
Quartus® Prime Pro Edition synthesis results or third-party netlist files in the
Quartus® Prime software.
You can view results after Analysis and Elaboration for designs that use any supported
Quartus® Prime design entry method, including Verilog HDL Design Files (.v), SystemVerilog Design Files (.sv), VHDL Design Files (.vhd), AHDL Text Design Files (.tdf), or schematic Block Design Files (.bdf).
You can also view the hierarchy of atom primitives (such as device logic cells and I/O ports) for designs that generate Verilog Quartus Mapping File (.vqm) or Electronic Design Interchange Format (.edf) files through a synthesis tool.
The RTL Viewer displays a schematic view of the design netlist after Analysis and Elaboration or after the
Quartus® Prime software performs netlist extraction, but before technology mapping and synthesis or fitter optimizations. This view a preliminary pre-optimization design structure and closely represents the original source design.
For designs synthesized with
Quartus® Prime Pro Edition synthesis, this view shows how the
Quartus® Prime software interprets the design files.
For designs synthesized with a third-party synthesis tool, this view shows the netlist that the synthesis tool generates.
To run the RTL Viewer for a
Quartus® Prime project,
first analyze the design to generate an RTL netlist. To analyze the design and
generate an RTL netlist, click Processing > Start > Start Analysis & Elaboration. You can also perform a full compilation on any process that includes
the initial Analysis and Elaboration stage of the
Quartus® Prime compilation flow.
To open the RTL Viewer, click Tools > Netlist Viewers > RTL Viewer.