Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
Public
Document Table of Contents

1.18. Power Management

Intel® Agilex™ devices capitalize on the advanced Intel 10-nm FinFET process technology, the second generation Intel® Hyperflex™ core architecture, power gating, and several optional power reduction techniques to reduce total power consumption by as much as 40% compared to previous generation high-performance Intel® Stratix® 10 devices.

Intel® Agilex™ standard power devices (-V) are SmartVID devices. The core voltage supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus voltage regulator dedicated to that Intel® Agilex™ device. Use of a PMBus voltage regulator for each SmartVID (-V) device is mandatory; not optional. A code is programmed into each SmartVID device during manufacturing that allows the PMBus voltage regulator to operate at the optimum core voltage to meet the device performance specifications. There are Intel® Agilex™ device options are available that used a fixed core voltage. These devices are designated (-F) and are available with limited core speed options.

Additionally, power gating reduces static power of unused resources in the FPGA by powering them down. The Intel® Quartus® Prime software automatically powers down specific unused resource blocks such as DSP and M20K blocks at configuration time.

The optional power reduction techniques in Intel® Agilex™ devices include Low Static Power Devices. Intel® Agilex™ devices are available that provide lower static power than the SmartVID standard power devices, while maintaining device performance

Furthermore, Intel® Agilex™ devices features industry-leading low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 50% less power than the equivalent soft logic implementations.