1.12. I/O PLLs
Intel® Agilex™ FPGAs contain I/O PLLs available for general purpose use in the core fabric and for simplifying the design of external memory interfaces and high-speed LVDS interfaces. The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank contains two I/O Bank I/O PLLs and one fabric-feeding I/O PLL. This placement makes it easier to close timing because the I/O PLLs are tightly coupled with the I/Os that need to use them. The I/O PLLs can be used for general purpose applications in the core such as clock network delay compensation and zero-delay clock buffering.