Intel® Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 1/10/2023
Public
Document Table of Contents

1.11. Core Clock Network

Core clocking function in Intel® Agilex™ devices employs the use of programmable clock tree synthesis.

This technique uses dedicated clock tree routing and switching circuits, and allows the Intel® Quartus® Prime software to create the exact clock trees required for your design. Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock tree and allows greater clocking flexibility in the core while still maintaining backwards compatibility with legacy global and regional clocking schemes.

The core clock network in Intel® Agilex™ devices supports the second generation Intel® Hyperflex™ core architecture. It also supports the hard memory controllers up to 3,200 Mbps for DDR4 with a quarter rate transfer to the core and the hard memory controllers up to 5,600 Mbps for DDR5. The core clock network is supported by dedicated clock input pins and integer I/O PLLs.

Did you find the information on this page useful?

Characters remaining:

Feedback Message