Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.6. Intel® Hyperflex™ Core Architecture

Intel® Agilex™ FPGAs and SoCs are based on a core fabric featuring the second generation Intel® Hyperflex™ core architecture. The second generation Intel® Hyperflex™ core architecture delivers on average 50% higher clock frequency performance or up to 40% lower power compared to previous generation of high-end Intel FPGAs.

Along with this performance breakthrough, the Intel® Hyperflex™ core architecture delivers a number of advantages including:

  • Higher Throughput: Delivers on average 50% higher core clock frequency performance of designs in previous generation high-end FPGAs to obtain throughput breakthroughs
  • Improved Power Efficiency: Uses reduced IP size enabled by Intel® Hyperflex™ architecture to consolidate designs which previously spanned multiple devices into a single device, thereby reducing power by up to 40% versus previous generation devices
  • Greater Design Functionality: Uses faster clock frequency to reduce bus widths and reduce IP size, freeing up additional FPGA resources to add greater functionality
  • Increased Designer Productivity: Boosts performance with less routing congestion and fewer design iterations using Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure

In addition to the traditional user registers found in the Adaptive Logic Modules (ALMs), the Intel® Hyperflex™ core architecture introduces additional bypassable registers distributed throughout the fabric of the FPGA. These additional registers, called Hyper-Registers are available on every interconnect routing segment and at the inputs of all functional blocks. In the second generation Intel® Hyperflex™ core architecture, the number of registers have been optimized to improve both timing closure time and fabric area.

Figure 4. Bypassable Hyper Register

The Hyper-Registers enable the following key design techniques to achieve on average 45% core performance increases:

  • Fine grain Hyper-Retiming to eliminate critical paths
  • Zero latency Hyper-Pipelining to eliminate routing delays
  • Flexible Hyper-Optimization for best-in-class performance

By implementing these techniques in your design, the Hyper-Aware design tools automatically make use of the Hyper-Registers to achieve maximum core clock frequency.

Figure 5.  Intel® Hyperflex™ Core Architecture

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