Serial Lite III Streaming Intel® FPGA IP User Guide

Download PDF
ID 683330
Date 11/01/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Intel® Arria® 10 Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Intel® Stratix® 10 Devices 3.4.3. Parameter Settings for Intel® Arria® 10 Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Intel® Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Intel® Arria® 10 Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Intel® Stratix® 10 Devices 5.9.3. Signals for Intel® Arria® 10 Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Intel® Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Intel® Arria® 10, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Intel® Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Intel® Arria® 10, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type Intel® Stratix® 10 and Intel® Arria® 10 Devices Stratix® V and Arria® V Devices
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

6.4.1. Choosing TX PLL Type

These are the guidelines for choosing the appropriate type of TX PLL.

Intel® Stratix® 10 and Intel® Arria® 10 Devices

Table 40.   Intel® Stratix® 10 L-tile/H-tile Transceiver PLL Data Rate PerformanceFor Intel® Quartus® Prime Pro Edition, configure the ATX PLL and fPLL parameter VCCR_GXB and VCCT_GXB supply voltage for the Transceiver to 1.1V and re-generate the IP cores when using data rate more then 15 Gbps.
Number of Lanes 10.3125 G 12.5 G 17.4 G 28 G
1 – 6 x1 – ATX/fPLL/CMU x1/x6/xN – ATX/fPLL x1/x6/xN – ATX x1/x4 — ATX
x6/xN – ATX/fPLL
7 – 24 x1 – ATX/fPLL/CMU if using multiple PLLs x1/x6/xN – ATX/fPLL if using 1 or multiple PLLs x1/x6/xN – ATX if using multiple PLLs (use multiple PLLs as xN with 1.12 V can only support up to 16 G) Not supported in Serial Lite III Streaming IP core.
x6/xN – ATX/fPLL if using 1 or multiple PLLs
Table 41.   Intel® Arria® 10 PLL Data Rate Performance
Number of Lanes 10.3125 G 12.5 G 17.4 G
1 – 6 x1 – ATX/fPLL/CMU x1/x6/xN – ATX/fPLL x1/x6/xN – ATX
x6/xN – ATX/fPLL
7 – 24 x1 – ATX/fPLL/CMU if using multiple PLLs x1/x6/xN – ATX/fPLL if using 1 or multiple PLLs x1/x6/xN – ATX if using multiple PLLs (use multiple PLLs as xN with 1.12 V can only support up to 16 G)
x6/xN – ATX/fPLL if using 1 or multiple PLLs

For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), place the ATX PLLs with the gap of seven ATX PLLs apart (skip 6). For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), place the ATX PLLs with the gap of four ATX PLLs apart (skip 3). If these spacing rules are violated, the Intel® Quartus® Prime issues a critical warning. The maximum channel span of a xN clock network is two transceiver banks above and two transceiver banks below the bank that contains the driving PLL and the master CGB. You can use a maximum of 30 channels in a single-bonded or non-bonded xN group. The maximum data rate supported by the xN clock network while driving channels in either the bonded or non-bonded mode depends on the voltage used to drive the transceiver banks and the transceiver speed grade.

Stratix® V and Arria® V Devices

The Serial Lite III Streaming Intel® FPGA IP core in Stratix® V and Arria® V devices allow a selection of PLL type for use inside the transmit and receive PMA blocks. The IP parameter editor in Intel® Quartus® Prime Standard Edition allows you to select either a CMU PLL or an ATX PLL. The CMU PLL is more suitable for lower lane data rates, while the ATX PLL is better for higher lane data rates. The supported data rates for the CMU PLL and ATX PLL are provided in Tables 1 ( Stratix® V) and 2 ( Arria® V GZ). These tables list the maximum lane data rates per transceiver speed grade. For example, if your design requires a 14.1 Gbps lane rate, you need to use an ATX PLL and select a Transceiver Speed Grade 1 device.

Table 42.   Stratix® V CMU and ATX PLL Supported Data RatesFor more information about the Stratix® V devices, refer to the device data sheet.
Symbol/ Description Conditions Transceiver Speed Grade 1 (Mbps) Transceiver Speed Grade 2 (Mbps) Transceiver Speed Grade 3 (Mbps)
Min Typ Max Min Typ Max Min Typ Max
CMU PLL Supported Data Range _ 600 _ 12500 600 _ 12500 600 _ 8500
ATX PLL Supported Data Range VCO

Post-divider L=2

8000 _ 14100 8000 _ 12500 8000 _ 8500
L=4 4000 _ 7050 4000 _ 6600 4000 6600
L=8 2000 _ 3525 2000 _ 3300 2000 _ 3300
Table 43.   Arria® V GZ CMU and ATX PLL Supported Data RatesFor more information about the Arria® V GZ devices, refer to the device data sheet.
Symbol/ Description Conditions Transceiver Speed Grade 2 (Mbps) Transceiver Speed Grade 3 (Mbps)
Min Typ Max Min Typ Max
CMU PLL Supported Data Range _ 600 _ 12500 600 _ 10312.5
ATX PLL Supported Data Range VCO

Post-divider L=2

8000 _ 12500 8000 _ 10312.5
L=4 4000 _ 6600 4000 6600
L=8 2000 _ 3300 2000 _ 3300
Related Information
Level Two Title