Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2. Transmission Overheads and Lane Rate Calculations

The Serial Lite III Streaming IP core lane data rate (transceiver data rate) is composed of the input data rate and transmission overheads.

Lane Rate = Input Data Rate + Transmission Overheads (10% of Input Data Rate)

The parameter editor uses the above equation to ensure that the lane rate is within the maximum supported transceiver lane rates. This puts an upper limit on the input data rate or the user clock frequency, where the user clock frequency equates to:

User Clock Frequency = Input Data Rate/64 

The Serial Lite III Streaming IP core uses the Interlaken protocol for transferring data and therefore incurs encoding and metaframe overheads.

In the standard clocking mode, the IP core employs an fPLL or I/O PLL for clock generation. To ensure that the fPLL or I/O PLL generates the clock as close as possible to the user clock that you have specified, the fPLL or I/O PLL incurs additional overheads. The transmission overheads can thus be derived in the following functions:

Transmission Overheads = Maximum (Interlaken Overheads + fPLL or I/O PLL Overheads) 
where Interlaken Overheads = [MetaFrame Length /(MetaFrame length - 4)]* 67/64

Therefore, the IP core standard clocking mode lane data rate can be calculated with the following equation:

Lane Data Rate in Standard Clocking Mode = (User Clock Frequency × 64) × 1.1
where 1.1 is referring to additional 10% of Input Data Rate as the transmission overheads.

In the advanced clocking mode, the transmission overheads equals the Interlaken overheads because no fPLL or IOPLL is present. Therefore, the lane rate in advanced clocking mode equals:

Lane Rate = Input Data Rate × Interlaken overheads 
Tip: You can obtain the Serial Lite III Streaming IP Core Function Data Efficiency Calculator for 28 nm Intel FPGA devices from your local Intel sales representative.
Table 21.  Example of Transmission Overheads and Lane Rate Calculations per Clocking ModesThis example is based on 12.5 Gbps lane rate with metaframe length of 200.
Parameters Standard Clocking Mode Advanced Clocking Mode
Lane rate 12.5 Gbps 12.5 Gbps
Interlaken overheads

[Metaframe length/(metaframe length - 4)] * (67/64)

200 / (200 - 4) * (67/64) = 1.06824

[Metaframe length/(metaframe length - 4)] * (67/64)

200 / (200 - 4) * (67/64) = 1.06824

Transmission overheads 1.1

Interlaken overheads

Input data rate

Lane rate/transmission overheads

12.5 Gbps/1.1 = 11.364 Gbps

Lane rate/transmission overheads

12.5 Gbps/1.06824 = 11.701 Gbps

User clock frequency

Input data rate/64

11.364 Gbps/64 = 177.5625 MHz

Input data rate/64

11.701 Gbps/64 = 182.828 MHz