Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 11/01/2021
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Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Intel® Arria® 10 Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Intel® Stratix® 10 Devices 3.4.3. Parameter Settings for Intel® Arria® 10 Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Intel® Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Intel® Arria® 10 Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Intel® Stratix® 10 Devices 5.9.3. Signals for Intel® Arria® 10 Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Intel® Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Intel® Arria® 10, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Intel® Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Intel® Arria® 10, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

2.3. Performance and Resource Utilization

Serial Lite III Streaming Intel® FPGA IP in Intel® Stratix® 10 devices support the following transceiver tiles for each device speed grade and data rate:
Table 2.   Serial Lite III Streaming IP Transceiver Tiles Support in Intel® Stratix® 10 Devices
Data Rate Core Speed Grade Maximum Supported Lanes
L-Tile Transceiver H-Tile Transceiver E-Tile Transceiver
17.4 Gbps 1 24 24 24
2 22 24 24
3 18 20 24
25.0 Gbps 1 6 8 12
2 4 6 8
28.0 Gbps 1 N/A 4 4
2 N/A 2 1
Table 3.   Serial Lite III Streaming IP Performance and Resource Utilization with L-Tile Transceiver in Intel® Stratix® 10 DevicesThese typical resources and expected performance for different Serial Lite III Streaming IP variants are obtained using the Intel® Quartus® Prime Pro Edition software targeting the Intel® Stratix® 10 1SG280LU3F50E1VG device for 17.4 Gbps data rate and 1SG280LU2F50E1VG device for 25 Gbps data rate. The resource utilization numbers are the same for ECC enabled and disabled.
Direction Clocking Mode Data Lanes Per-Lane Data Rate (Mbps) ALMs Primary Secondary M20K
Source Standard 24 17400 11675 13622 776 49
Standard 6 25000 3160 3644 215 13
Advance 24 17400 11691 13571 919 49
Advance 6 25000 3139 3687 181 13
Sink Standard 24 17400 5181 7532 2065 49
Standard 6 25000 1463 2009 513 13
Advance 24 17400 4485 6994 2359 0
Advance 6 25000 1245 1792 629 0
Duplex Standard 24 17400 15793 19074 2913 98
Standard 6 25000 4299 5123 698 26
Advance 24 17400 14984 18880 2976 49
Advance 6 25000 4025 4980 812 13
Table 4.   Serial Lite III Streaming IP Performance and Resource Utilization with H-Tile Transceiver in Intel® Stratix® 10 DevicesThese typical resources and expected performance for different Serial Lite III Streaming IP variants are obtained using the Intel® Quartus® Prime Pro Edition software targeting the Intel® Stratix® 10 1SG280HU3F50E1VG device for 17.4 Gbps data rate, 1SG280HU2F50E1VG device for 25 Gbps data rate, and 1SG280HU1F50E1VG device for 28 Gbps data rate. The resource utilization numbers are the same for ECC enabled and disabled.
Direction Clocking Mode Data Lanes Per-Lane Data Rate (Mbps) ALMs Primary Secondary M20K
Source Standard 24 17400 11708 13604 851 49
Standard 8 25000 5013 5048 296 17
Standard 4 28000 2652 2803 193 9
Advance 24 17400 11638 13636 817 49
Advance 8 25000 4919 5195 324 17
Advance 4 28000 2649 2830 176 9
Sink Standard 24 17400 5175 7732 1907 49
Standard 8 25000 2685 3063 666 17
Standard 4 28000 1367 1659 263 9
Advance 24 17400 4524 7045 2295 0
Advance 8 25000 2530 3009 761 0
Advance 4 28000 1371 1599 397 0
Duplex Standard 24 17400 15790 19353 2814 98
Standard 8 25000 6239 7332 949 34
Standard 4 28000 3391 3916 526 18
Advance 24 17400 15012 18941 3078 49
Advance 8 25000 6208 7174 987 17
Advance 4 28000 3312 3824 533 9
Table 5.   Serial Lite III Streaming IP Performance and Resource Utilization with E-Tile Transceiver in Intel® Stratix® 10 DevicesThese typical resources and expected performance for different Serial Lite III Streaming IP variants are obtained using the Intel® Quartus® Prime Pro Edition software targeting the Intel® Stratix® 10 1ST280EY3F55E1VG device for 17.4 Gbps data rate, 1ST280EY2F55E1VG device for 25 Gbps data rate, and 1ST280EY1F55E1VG device for 28 Gbps data rate. The resource utilization numbers are the same for ECC enabled and disabled.
Direction Clocking Mode Data Lanes Per-Lane Data Rate (Mbps) ALMs Primary Secondary M20K
Duplex Standard 24 17400 48277 59072 10903 194
Standard 12 25000 24026 28845 5717 73
Standard 4 28000 8596 9825 1904 34
Advance 24 17400 47516 58816 11321 145
Advance 12 25000 24460 28608 5265 98
Advance 4 28000 8377 9559 1823 25
Table 6.   Serial Lite III Streaming IP Performance and Resource Utilization for Intel® Arria® 10 DevicesThese typical resources and expected performance for different Serial Lite III Streaming IP variants are obtained using the Intel® Quartus® Prime Pro Edition software targeting the Intel® Arria® 10 (10AX115S1F45I1SGES) FPGA devices.
Direction Clocking Mode Maximum Supported Data Lanes Per-Lane Data Rate (Mbps) ECC ALMs Primary Secondary M20K
Source Standard 24 17400 2 Disabled 2613 5049 780 39
Standard 24 17400 2 Enabled 5961 9680 525 72
Advanced 24 17400 2 Disabled 3009 5240 570 39
Advanced 24 17400 2 Enabled 6065 9659 552 72
Sink Standard 24 17400 2 Disabled 3974 7550 1750 49
Standard 24 17400 2 Enabled 4065 7570 1632 50
Advanced 24 17400 2 Disabled 3297 5815 1580 0
Advanced 24 17400 2 Enabled 3275 5524 1870 0
Duplex Standard 24 17400 2 Disabled 6152 12511 2000 88
Standard 24 17400 2 Enabled 9313 16606 2193 122
Advanced 24 17400 2 Disabled 5833 10462 2146 39
Advanced 24 17400 2 Enabled 8868 14853 2112 72
Table 7.   Serial Lite III Streaming IP Performance and Resource Utilization for Stratix® V and Arria® V DevicesThese typical resources and expected performance for different Serial Lite III Streaming IP variants are obtained using the Intel® Quartus® Prime Standard Edition software targeting the Stratix® V GX (5SGXMA7H2F35C2) and the Arria® V GZ (5AGZME7K2F40I3L) FPGA devices.
Direction Clocking Mode Maximum Supported Data Lanes Per-Lane Data Rate (Mbps) ECC ALMs Primary Secondary M20K
Source Standard 24 10312.50 Disabled 5684 6114 46 39
Standard 24 10312.50 Enabled 11122 13422 271 72
Advanced 24 10312.50 Disabled 5680 6104 43 39
Advanced 24 10312.50 Enabled 11015 13418 239 72
Sink Standard 24 10312.50 Disabled 5499 9601 93 49
Standard 24 10312.50 Enabled 5517 9510 91 50
Advanced 24 10312.50 Disabled 4356 7757 43 0
Advanced 24 10312.50 Enabled 4356 7757 43 0
Duplex Standard 24 10312.50 Disabled 8742 15024 165 88
Standard 24 10312.50 Enabled 14045 22279 337 122
Advanced 24 10312.50 Disabled 7550 13211 74 39
Advanced 24 10312.50 Enabled 12606 20534 293 72
2 Available only with transceiver speed grade 1.
Level Two Title