Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

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5.3. Reset

Intel® Arria® 10, Stratix V and Arria V GZ Reset Scheme

Each core has a separate active high reset signal, core_reset, that asynchronously resets all logic in the core.

Each core also includes the Native PHY or Interlaken PHY IP reset signal, phy_mgmt_clk_reset. This reset signal must be on the same clock domain as the clock used to drive the reconfiguration controllers, phy_mgmt_clk. The Native PHY or Interlaken PHY IP core requires the assertion of this reset signal to synchronize with the reconfiguration controller reset signal.

Note: Intel recommends using the same reset signals for both the Native PHY or Interlaken PHY IP core and the reconfiguration controller.
When the phy_mgmt_clk_reset or core_reset signal is asserted on the source core, the sink deasserts the link_up_rx signal. However, there is no additional indication on the sink core whether the last transmitted burst has bad data. The source core reinitializes the internal reset sequence when the phy_mgmt_clk_reset or core_reset signal is deasserted. Once the internal reset sequence is complete, the core asserts the link_up_tx signal to indicate that the core initialization is complete and is ready to transmit user data.
Note: Intel recommends that you wait for an additional 30 µs on the source core before sending any valid Avalon streaming data cycle. This is to ensure that the sink core has sufficient time to assert the link_up_rx signal.

Intel® Stratix® 10 L-tile/H-tile Transceivers Reset Scheme

For Intel® Stratix® 10 L-tile/H-tile transceivers devices, the IP core uses the phy_mgmt_clk_reset signal to reset all the modules in the IP core and user_clock_reset signal to reset the user clock domain modules e.g. transmit and receive FIFO.

You may also trigger a reset to the IP core by writing into the reset controller register in the PHY:
  • Writing 1 to CSR address 0x02E2 bit 3 to initiate a TX digital reset and bit 1 to initiate a RX digital reset
  • Writing 1 to CSR address 0x02E2 bit 2 to initiate a TX analog reset and bit 0 to initiate a RX analog reset

Intel® Stratix® 10 E-tile Transceivers Reset Scheme

E-Tile transceivers have separate reset procedures for analog reset and digital reset.

You can use the PMA attribute code 0x0001 on the AVMM reconfiguration bus to enable or disable the PMA. Disabling the PMA puts it in reset. Digital reset can be asserted using the digital reset controller in the Native PHY IP.

Use the following guidelines to provide a proper reset to the IP core. These guidelines are applicable to Intel® Stratix® 10 L-tile/H-tile/E-tile transceivers devices:
  • Use the same reset signals for both the source and sink user clock domain modules.
  • Synchronize the user_clock_reset signals with phy_mgmt_clock_reset signal assertion.
  • Use the phy_mgmt_clk_reset signal to reset the configuration and status registers.
  • Ensure all clocks are toggling in a correct rate before de-asserting any reset signals.