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1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Intel® FPGA IP Evaluation Mode
3.3. Specifying IP Core Parameters and Options
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters
3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs
3.6. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3.7. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
3.8. Simulating
5.1. IP Architecture
5.2. Transmission Overheads and Lane Rate Calculations
5.3. Reset
5.4. Link-Up Sequence
5.5. Error Detection, Reporting, and Recovering Mechanism
5.6. CRC-32 Error Injection
5.7. FIFO ECC Protection
5.8. User Data Interface Waveforms
5.9. Signals
5.10. Accessing Configuration and Status Registers
5.1.1. Serial Lite III Streaming Source Core
5.1.2. Serial Lite III Streaming Sink Core
5.1.3. Serial Lite III Streaming IP Core Duplex Core
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Stratix® V, and Arria® V GZ Variations
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5.7. FIFO ECC Protection
In the Quartus II software version 13.1 and later, the Serial Lite III Streaming IP core can be protected from Single-Event Upset (SEU) changes using error correcting code (ECC) protection. You can enable this feature using the ECC protection option in the parameter editor. The ECC protection provides additional error status bits that tell you if the ECC was able to perform a correction from the SEU change or if an uncorrectable error has occurred.
Note: Enabling ECC protection incurs additional logic and latency overhead.