Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.2. Burst Mode

The Serial Lite III Streaming Intel® FPGA IP link operating in burst mode accepts bursts of data across the user interface and transmits each burst across the link as a discrete data burst.

Burst mode is appropriate for applications where the data stream is divided into bursts of data. An example of this application is uncompressed digital video where the data stream is divided into lines of display raster. This mode provides more flexibility to the clocking and also supports multiplexing of multiple data streams across the link.
Important: The minimum required gap between bursts is 1 user clock cycle on the transmit side. Therefore, you must provide one extra user clock cycle between an end of burst and the start of the next burst. The Serial Lite III Streaming Intel® FPGA IP allows you to select between 1 or 2 burst gap. To connect the IP of version 15.1 to IP of the previous version, you must select a burst gap of 2 for backward compatibility.