Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021
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3.8.3. Simulating and Verifying the Design

By default, the parameter editor generates simulator-specific scripts containing commands to compile, elaborate, and simulate Intel FPGA IP models and simulation model library files. You can copy the commands into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and simulating your design and testbench.

Table 18.   Intel FPGA IP Core Simulation Scripts

Simulator

File Directory

Device Family

Script

ModelSim*

QuestaSim*

<variation name>_ sim/mentor

Stratix V

Arria V GZ

msim_setup.tcl 3

<variation name> /sim/mentor Intel® Arria® 10

Intel® Stratix® 10

VCS*

<variation name>_ sim/synopsys/vcs

Stratix V

Arria V GZ

vcs_setup.sh

<variation name> /sim/synopsys/vcs Intel® Arria® 10

Intel® Stratix® 10

VCS* MX

<variation name>_ sim/synopsys/vcsmx

Stratix V

Arria V GZ

vcsmx_setup.sh

synopsys_sim.setup

<variation name> /sim/synopsys/vcsmx Intel® Arria® 10

Intel® Stratix® 10

Riviera-PRO*

<variation name>_ sim/aldec

Stratix V

Arria V GZ

rivierapro_set.tcl

<variation name> /sim/aldec Intel® Arria® 10

Intel® Stratix® 10

Note: This simulator is not supported for E-Tile transceiver.
Xcelium*

<variation name>_ sim/xcelium

Intel® Arria® 10

Intel® Stratix® 10

xcelium_setup.sh
3 If you did not set up the EDA tool option— which enables you to start third-party EDA simulators from the Intel® Quartus® Prime software—run this script in the ModelSim* or QuestaSim* simulator Tcl console (not in the Intel® Quartus® Prime software Tcl console) to avoid any errors.