Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

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Document Table of Contents

5.1.2. Serial Lite III Streaming Sink Core

The sink core consists of five major functional blocks:

  • L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY IP RX core for Intel® Arria® 10 - Interlaken mode
  • Interlaken PHY v18.1 IP RX core ( Stratix® V or Arria® V GZ devices)
  • Lane alignment module
  • Sink adaptation module (standard clocking mode only)
  • Sink application module
  • Clock generator (in the standard clocking mode for Intel® Arria® 10, Stratix® V, and Arria® V GZ devices)