Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

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3.3.2. Intel® Arria® 10 Designs

If your design targets the Intel® Arria® 10 devices:

  • The parameter editor displays a message about the required output clock frequency of the external TX PLL IP clock. For source or duplex modes, connect the Transceiver PHY Reset Controller to the TX PLL to ensure the appropriate HSSI power-up sequence.
  • For source only Intel® Arria® 10 implementations, the parameter editor does not provide the transceiver reference clock frequency because the user is expected to provide the transmit serial clock. If you use an on-chip PLL to generate the transmit serial clock, you can use the same PLL reference clock frequency that you provide to the core in the sink direction, operating at the same user clock frequency (or equivalent transceiver lane data rate).
  • The Serial Lite III Streaming Intel® Arria® 10 FPGA IP expects the user to provide the transmitter's serial clock. If you compile the IP without the proper serial clock, the Intel® Quartus® Prime Compiler issues a compilation error.

  • When generating the example testbench, the Serial Lite III Streaming Intel® Arria® 10 FPGA IP instantiates an external transceiver ATX PLL for the transmit serial clock based on the required user clock only when configured in sink or duplex mode. The transceiver ATX PLL core is configured with the transceiver reference clock specified in the parameter editor and transmit serial clock.
  • To generate the Serial Lite III Streaming Intel® Arria® 10 FPGA IP example testbench using the parameter editor, select Generate Example Designs > <directory_name> . Intel recommends that you generate the Intel® Arria® 10 simulation testbench for the sink or duplex direction.