Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

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Document Table of Contents Source Adaptation Module

This module provides adaptation logic between the application module and the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP core or Transceiver Native PHY in Intel® Arria® 10 devices or Interlaken PHY v18.1 IP (Stratix V and Arria V GZ devices) core. The adaptation module performs the following functions:

  • Rate adaptation—includes a dual-clock FIFO buffer to cushion the Interlaken PHY v18.1 IP core's burst read requests and to provide a streaming user write interface. The FIFO also transfers streaming data between the user_clock and tx_coreclkin clock domains.
  • Control signal translation—include state machines that map the control signal semantics on the framing interface4 to the semantics of the Transceiver Native PHY or Interlaken PHY v18.1 IP core TX interface.
  • Non-user idle insertion—inserts non-user idle control words in the absence of user data to manage the minimum data rate requirements of the Interlaken protocol. The control words are removed by the sink adaptation module in the Serial Lite III Streaming IP core link partner.
  • ECC correction and ECC fatal error detection
4 The framing interface is to frame every data burst with the Start of Burst, Sync, and End of Burst, and sequence them to the PHY interface.