Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

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Document Table of Contents

8.2.1. Source Core Link Debugging

Figure 28. Source Core Link Debugging Flow Chart
Table 49.  Source Link Debugging Signals ( Intel® Arria® 10, Intel® Stratix® 10, Arria® V GZ, and Stratix® V devices)

Signal Name


( Intel® Arria® 10, Arria® V GZ, and Stratix® V)


( Intel® Stratix® 10)



Top level port

Top level port

The core asserts this signal to indicate that initialization sequence is complete and the core is ready to transmit the data.


Native PHY wrapper port

Top level port

This active high signal indicates that the transceivers are locked to the reference clock.


Native PHY wrapper port

(Encrypted) Soft PHY port

This active high signal indicates that the reset sequence for the source PCS is complete and is ready to accept data.


Native PHY wrapper port

PHY top port

This active high signal indicates that all the lanes are bonded by the Native PHY or Interlaken PHY IP core. This signal should be properly asserted for normal operation. A rapidly toggling signal indicates that the source FIFO is having either too much or too little data, or the core reset is having issues.


/source/Interlaken_phy_ip_tx/ sv_ilk_inst

(for Stratix V devices only)


Source transceiver calibration status. This active high signal can be used for debugging if the reconfiguration controller is actively calibrating during the initialization sequence.