Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.10. Accessing Configuration and Status Registers

The Avalon memory-mapped PHY management block within the Interlaken PHY IP core or Native PHY IP core includes master and slave interfaces. This component acts as a bridge. It transfers commands received on its Avalon memory-mapped slave interface to its Avalon memory-mapped port. This interface manages PCS and PMA modules, resets, error handling, and serial loopback controls. Refer to Configuration and Status Registers for more information of registers that you can access using the Avalon memory-mapped PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.