6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
The Serial Lite III Streaming Intel® FPGA IP has two clocking options to support a variety of streaming applications:
- Standard Clocking Mode (SCM):
- In this clocking mode, there is no PPM difference (mesochronous system) in both source and sink cores for Intel® Arria® 10, Stratix® V, and Arria® V devices. The user interface clock and IP core clock are generated from the same clock source in both source and sink cores.
- For Intel® Stratix® 10 devices, this clocking mode is the same as advanced clocking mode for source core. For sink core, a user interface clock is required to drive the adaptation module in the core. To design a mesochronous system, Intel recommends to use the same clock source for transceiver input clock in both source and sink cores.
- Advanced Clocking Mode (ACM):
- In this clocking mode, for source core, you are required to manage any PPM difference between the user interface logic domain and the transceiver clock domain by throttling the data input or use the same clock source for user interface and transceiver clock domains. The IP does not support any PPM tolerance between the user interface domain and the transceiver clock domain. For sink core, there is no PPM differences because you are expected to use the recovered clock for user interface logic.
The following sections describe the clocking architectures for Intel® Stratix® 10, Intel® Arria® 10, Stratix® V, and Arria® V GZ devices.