50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Public
Document Table of Contents
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1. About This IP Core

Updated for:
Intel® Quartus® Prime Design Suite 22.1

Interlaken is a high‑speed serial communication protocol for chip‑to‑chip packet transfers. The 50G Interlaken Intel® FPGA IP implements the Interlaken Protocol Specification, Revision 1.2 . It supports eight lanes at a lane rate of 6.25 gigabits per second (Gbps), on Stratix® V, Arria® V GZ, and Intel® Arria® 10 devices, providing raw bandwidth of 50 Gbps.

Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The 50G Interlaken IP core incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.

Figure 1. Typical Interlaken Application