50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents 50G Interlaken IP Core TX MAC

The 50G Interlaken IP core TX MAC performs the following functions:

  • Inserts burst and idle control words in the incoming data stream. Burst delineation allows packet segmentation in the Interlaken protocol.
  • Performs flow adaption of the data stream, repacking the data to ensure the maximum number of words is available on each valid clock cycle.
  • Calculates and inserts CRC24 bits in all burst and idle words.
  • Inserts calendar data in all burst and idle words.
  • Stripes the data across the PCS lanes. Configurable order, default is MSB of the data goes to lane 0.
  • Buffers data between the application and the TX PCS block in the TX FIFO buffer. The TX PCS block uses the FIFO buffer to recover bandwidth when the number of words delivered to the transmitter is less than the full width.