50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

2.3. Files Generated for Arria V GZ and Stratix V Variations

The Quartus® Prime software generates multiple files during generation of your 50G Interlaken IP core Arria V GZ or Stratix V variation.

Figure 4. IP Core Generated Files

For 50G Interlaken IP cores that target a non- Intel® Arria® 10 device, if you select the Verilog HDL for synthesis and simulation models and turn on Generate example design, the demonstration testbench and example design files are located in <your_ip> _testbench/ilk_core _50g /testbench.