50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

8. Advanced Parameter Settings

Advanced users can further customize the 50G Interlaken IP core by modifying hidden parameters that are not displayed in the 50G Interlaken parameter editor. These parameters can only be modified in the Verilog RTL instantiation in the generated ilk_core _50g .sv file and the instantiation of the 50G Interlaken IP core in the top level design file.

The following topics describe the hidden parameters and tell you how to modify their values.