50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

A. Performance and Fmax Requirements for 40G Ethernet Traffic

To achieve 40G Ethernet line rates through the application interface of your 50G Interlaken IP core, you must run the transmit side and receiver side user interface clocks tx_usr_clk and rx_usr_clk at a minimum frequency of 200 MHz.

The following discussion describes the packet rate calculation that supports this requirement.

Figure 23. Interlaken Ethernet Packet

To transmit a minimum size (64-byte) Ethernet packet, the Interlaken link transmitter must send 672 bits of data.

To support an Ethernet line rate of 40Gb/s, the Interlaken link must process 400 bits in 10ns. The following calculation derives the required clock frequency.

This packet rate requires that the user interface handle one packet per two cycles if the operating clock runs at 200 MHz.

The following figures explain the derivation of the minimum frequency requirements.

Figure 24. Packet Processing Requirements

A 65-byte packet comprises (65 + 20) x 8 = 680 bits. Therefore, for traffic that consists mainly of 65-byte packets, the most inefficient traffic possible, the user interface must handle:

40 x 1,000,000,000 bits/sec ÷ 680 = 58.8 Million packets/sec, or one packet every 17 ns.

Case 2 in the figure shows that the user interface requires three cycles to process each 65-byte packet. At 200 MHz, three cycles take 15 ns, which is a sufficiently small amount of time.

The same calculations applied to lower frequencies yield an average time per packet that is not sufficiently short. Therefore, 200 MHz is the recommended frequency for the two user data transfer interface clocks in your 50G Interlaken IP core.