50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Public
Document Table of Contents

4.3.1. 50G Interlaken IP Core Clock Signals

Table 9.   50G Interlaken IP Core Clocks

Clock Name

Description

pll_ref_clk

Reference clock for the RX CDR PLL in IP core variations that target an Intel® Arria® 10 device. Reference clock for the RX CDR PLL and the TX transceiver PLL in all other variations.

tx_serial_clk[NUM_LANES–1:0]

Clocks for the individual transceiver channels in 50G Interlaken IP core variations that target an Intel® Arria® 10 device.

rx_usr_clk

Clock for the receive application interface.

tx_usr_clk

Clock for the transmit application interface.

mm_clk

Management clock for 50G Interlaken IP core register access.

reconfig_clk

Management clock for Intel® Arria® 10 hard PCS register access, including access for Intel® Arria® 10 transceiver reconfiguration and testing features.

If you choose to instantiate the optional out-of-band flow control blocks, your 50G Interlaken IP core has additional clock domains.