50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Public
Document Table of Contents
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1.1. Features

The 50G Interlaken IP core has the following features:

  • Compliant with the Interlaken Protocol Specification, Revision 1.2.
  • Supports eight serial lanes in configurations that provide up to 50 Gbps raw bandwidth.
  • Supports per‑lane data rate of 6.25 Gbps using Intel® on‑chip high‑speed transceivers.
  • Supports dynamically configurable BurstMax and BurstMin values.
  • Supports Packet mode and Interleaved (Segmented) mode for user data transfer.
  • Supports up to 256 logical channels in out‑of‑the‑box configuration.
  • Supports optional user‑controlled in‑band flow control with 1, 2, 4, 8, or 16 16‑bit calendar pages.
  • Supports optional out‑of‑band flow control blocks.