50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Public
Document Table of Contents

5.6.1. Transceiver Reconfiguration Controller Interface Signals

50G Interlaken IP core variations that target an Arria V or a Stratix V device require an external reconfiguration controller to function correctly in hardware. 50G Interlaken IP core variations that target an Arria 10 device include a reconfiguration controller block and do not require an external reconfiguration controller.

Table 16.   50G Interlaken IP Core Arria V and Stratix V Transceiver Reconfiguration Controller Interface Signals

Signal Name

Direction

Width (Bits)

Description

reconfig_to_xcvr

Input

70 bits per reconfiguration interface.

Bus from the external transceiver reconfiguration controller to the 50G Interlaken IP core. The bus includes signals from multiple transceiver reconfiguration interfaces. The reconfiguration controller has one interface to control each transceiver channel (one per Interlaken lane) plus one interface to control each TX PLL configured in the IP core. The width of each reconfiguration controller output reconfiguration interface is 70 bits.

reconfig_from_xcvr

Output

46 bits per reconfiguration interface

Bus to the external transceiver reconfiguration controller from the 50G Interlaken IP core. The bus includes signals for multiple reconfiguration interfaces of the transceiver reconfiguration controller. The reconfiguration controller has one interface for each transceiver channel (one per Interlaken lane) plus one interface for each TX PLL configured in the IP core. The width of each reconfiguration controller input reconfiguration interface is 46 bits.