50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents Generating the Reconfiguration Controller

You can use the IP Catalog to generate an Intel® Transceiver Reconfiguration Controller.

In the Transceiver Reconfiguration Controller parameter editor, you select the features of the transceiver that can be dynamically reconfigured. However, you must ensure that the following two features are turned on:

  1. Enable PLL calibration
  2. Enable Analog controls

You must also set the value of the Number of reconfiguration interfaces parameter. Each TX PLL requires its own reconfiguration interface, whether or not you intend to reconfigure it. The following formula determines the correct number of reconfiguration interfaces:



  • NUMBER_OF_LANES is the total number of physical lanes used in your implemented design.
  • NUMBER_OF_TX_PLLs is the total number of transceiver blocks (number of TX PLLs) used in your design.

For example, for a design that includes an Interlaken variation that is configured in two transceiver blocks, you must set Number of reconfiguration interfaces to the value of 10.