50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

4.6.3. In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface

The 50G Interlaken IP core receiver logic decodes incoming control words (both Burst control words and Idle control words) on the incoming Interlaken link, extracts the calendar pages from the In-Band Flow Control bits, and assembles them into the irx_calendar output signal.

The 50G Interlaken IP core receives the most significant calendar page in a control word with the Reset Calendar bit set, indicating the beginning of the calendar page sequence. The mapping of bits from the control words to the irx_calendar output signal is consistent with the mapping of bits from the itx_calendar input signal to the control words.

On the RX side, your application is responsible for mapping the calendar pages to the corresponding channels, according to any interpretation agreed upon with the Interlaken link partner application in sideband communication. On the TX side, your application is responsible for throttling the data it transfers to the TX user data transfer interface, in response to the agreed upon interpretation of the irx_calendar bits.