50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

7.3. PRBS Generation and Validation

The 50G Interlaken IP core supports generation and validation of several predetermined pseudo-random binary sequences (PRBS) for Interlaken link testing.

Table 20.  PRBS Polynomials Available in the 50G Interlaken IP Core
Pattern Name Polynomial Defined in Interlaken Specification Available in 50G Interlaken IP Core Variations with Target Device Family
Arria V or Stratix V Intel® Arria® 10
PRBS7 x7 + x6 + 1 Yes Yes No
PRBS9 x9 + x5 +1 No Yes Yes
PRBS15 x15 + x14 +1 No No Yes
PRBS23 x23 + x18 + 1 Yes Yes Yes
PRBS31 x31 + x28 + 1 Yes Yes Yes

For instructions to activate and use the PRBS test feature in your 50G Interlaken IP core IP core, refer to one of the following two topics: