50G Interlaken Intel® FPGA IP User Guide

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ID 683217
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 50G Interlaken IP Core 3. 50G Interlaken IP Core Parameter Settings 4. Functional Description 5. 50G Interlaken IP core Signals 6. 50G Interlaken IP Core Register Map 7. 50G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 50G Interlaken IP core 10. 50G Interlaken Intel® FPGA IP User Guide Archives 11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide A. Performance and Fmax Requirements for 40G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Raw Aggregate Bandwidth
2. Getting Started With the 50G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 50G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 50G Interlaken IP Core Parameter Settings x
3.1. Meta Frame Length in Words 3.2. Enable Native PHY Debug Master Endpoint (NPDME) 3.3. Transceiver Reference Clock Frequency 3.4. Number of Calendar Pages 3.5. TX Scrambler Seed 3.6. Transfer Mode Selection
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. 50G Interlaken IP Core Transmit Path 4.6. 50G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 50G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.5. 50G Interlaken IP Core Transmit Path x
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples 4.5.2. 50G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.5.3. 50G Interlaken IP Core Transmit Path Blocks
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples x
4.5.1.1. 50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.5.1.2. 50G Interlaken IP Core Packet Mode Operation Example 4.5.1.3. 50G Interlaken IP Core Back-Pressured Packet Transfer Example
4.5.3. 50G Interlaken IP Core Transmit Path Blocks x
4.5.3.1. 50G Interlaken IP Core TX Transmit Buffer 4.5.3.2. 50G Interlaken IP Core TX MAC 4.5.3.3. 50G Interlaken IP Core TX PCS 4.5.3.4. 50G Interlaken IP Core TX PMA
4.6. 50G Interlaken IP Core Receive Path x
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples 4.6.2. 50G Interlaken IP Core RX Errored Packet Handling 4.6.3. In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface 4.6.4. 50G Interlaken IP Core Receive Path Blocks
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples x
4.6.1.1. 50G Interlaken IP Core Receiver Side Example
4.6.2. 50G Interlaken IP Core RX Errored Packet Handling x
4.6.2.1. 50G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.6.4. 50G Interlaken IP Core Receive Path Blocks x
4.6.4.1. 50G Interlaken IP Core RX PMA 4.6.4.2. 50G Interlaken IP Core RX PCS 4.6.4.3. 50G Interlaken IP Core RX MAC 4.6.4.4. 50G Interlaken IP Core RX Regroup Block
5. 50G Interlaken IP core Signals x
5.1. 50G Interlaken IP Core Clock Interface Signals 5.2. 50G Interlaken IP Core Reset Interface Signals 5.3. 50G Interlaken IP Core User Data Transfer Interface Signals 5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 50G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 50G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Required User Clock Frequency 8.1.2. Counter Reset Bits 8.1.3. Include Temp Sense 8.1.4. RXFIFO Address Width 8.1.5. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) 8.1.6. Use ATX or CMU PLL 8.1.7. Lane Profile
9. Out-of-Band Flow Control in the 50G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic

7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices

To enable the IP core to generate PRBS output, for each Interlaken lane, you must program the relevant hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS polynomial. To enable the IP core to receive PRBS input, for each Interlaken lane, you must program the relevant hard PCS registers to enable the PRBS receiver clock and to select the expected PRBS polynomial, in addition to some bookkeeping tasks. If you perform your PRBS testing in loopback mode, you must enable the IP core to both generate and receive PRBS sequences. After you set the hard PCS registers for PRBS mode, you must perform a soft reset of the transceiver.

This section describes the register values you must program. For instructions to program the registers that activate the PRBS test feature in your Intel® Arria® 10 50G Interlaken IP core, refer to the hard PCS register information in the Intel® Arria® 10 Transceiver PHY User Guide. You program the hard PCS registers using the 50G Interlaken IP core Intel® Arria® 10 transceiver reconfiguration interface.

Table 22.  Programming the Hard PCS Registers in Intel® Arria® 10 Devices

To turn on the PRBS feature in the hard PCS for IP core variations that target an Intel® Arria® 10 device, you must program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are not accessible using the 50G Interlaken IP core management interface. You must access these registers through the Arria 10 transceiver reconfiguration interface of the 50G Interlaken IP core.

Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid modifying the other register fields.

TX Register Offset Bits Meaning Action
1 0x6 [2:0] TX test enable Set this field to the value of 3'b100 to enable the PRBS pattern generator in the transmitter.
[3] PRBS width select Set this bit to the value of 0 to specify that the PRBS width is 64 bits.
[7:6] Enable TX PRBS clock Set this field to the value of 2'b01 to enable the TX PRBS clock.
2 0x7 [2] Invert TX channels Set this bit to the value of 0 to specify that the outgoing PRBS be inverted, or set this bit to the value of 1 to specify that the outgoing PRBS not be inverted. The default value of this register field is 0. By default, the outgoing PRBS is inverted.
[5] Enable PRBS9 Set one of these bits to the value of 1, and the others to the value of 0, to select the TX polynomial.
[6] Enable PRBS15
[7] Enable PRBS23
3 0x8 [4] Enable PRBS31
RX Register Offset Bits Meaning Action
1 0xA [4] Invert RX channels Set this bit to the value of 0 to specify that the PCS should expect the incoming PRBS to be inverted, or set this bit to the value of 1 to specify that the PCS should not expect the incoming PRBS to be inverted. The default value of this bit is 0. In loopback mode, you should set this bit to match the setting in the PRBS transmitter.
[7] Enable RX PRBS clock Set this bit to the value of 1 to enable the RX PRBS clock.
2 0xB [1] Enable 10G PCS mode Set this bit to the value of 1 to specify the PCS is in 10G PCS mode.
[3:2] Verifier counter threshold Set this field to the value your design requires to ensure adequate lead time before the PRBS checker begins counting PRBS errors. The field value specifies the wait time in number of clk_rx_common clock cycles. A counter begins counting clk_rx_common clock cycles after the soft reset, and triggers the start of PRBS checking when the specified threshold is reached. This field has the following valid values:
  • 2'b00—Specifies the counter threshold (the wait time) is 127.
  • 2'b01—Specifies the counter threshold is 255.
  • 2'b10—Specifies the counter threshold is 511.
  • 2'b11—Specifies the counter threshold is 1023.
[5] Enable PRBS9 Set one of these bits to the value of 1, and the others to the value of 0, to select the expected polynomial.
[6] Enable PRBS15
[7] Enable PRBS23
3 0xC [0] Enable PRBS31
[1] Confirm 10G PCS mode Set this bit to the value of 1 to confirm the PCS is in 10G mode.
[3] PRBS width select Set this bit to the value of 0 to specify that the PRBS width is 64 bits.
4 0x13F [3:0] RX Deserializer width select Set this field to the value of 4'b1110 to specify that the data width after deserialization is 64 bits.

After you enable the IP core to generate or receive PRBS output, by setting the relevant register field values for each Interlaken lane, you must perform a soft reset of the transceiver transmitters and receivers. To perform a soft reset of the transceiver transmitters and receivers, on the 50G Interlaken IP core management interface, program bit [2] of the 50G Interlaken IP core RESET register at offset 0x13 with the value of 1. On the following mm_clk cycle, or later, program the bit 0x13[2] with the value of 0 to clear the reset. After you reset the transceivers and subsequently clear the reset bit, the IP core immediately begins transmitting PRBS output on the Interlaken link. You can check the receive PRBS status in the 50G Interlaken IP core PRBS status registers (RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT).

After your testing is complete, you must reset these register bits to their default values and perform the soft reset to enable normal operation.

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