50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

8.1.2. Counter Reset Bits

The Counter Reset Bits parameter (CNTR_BITS) specifies the counter configuration for the IP core internal reset sequence.

This parameter is not available in IP core variations that target an Intel® Arria® 10 device. In Intel® Arria® 10 variations, the size of the reset counters in the internal reset controller is set when the IP core is generated.

For simulation, set this parameter to the value of 6. For hardware testing, set this parameter to the value of 20.

The default value of this parameter is 20.