50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

4.6.2. 50G Interlaken IP Core RX Errored Packet Handling

The 50G Interlaken IP Core provides information about errored packets on the RX user data transfer interface through the following output signals:

  • irx_eopbits[3:0]—If this signal has the value of 4'b0001, an error indication arrived with the packet on the incoming Interlaken link: the EOP_Format field of the control word following the final burst of the packet on the Interlaken link has this value, which indicates an error and EOP.
  • irx_errThe 50G Interlaken IP Core checks the integrity of incoming packets on the Interlaken link, and reports the packet corruption errors it detects on the RX user data transfer interface in the irx_err output signal.

In both cases, the application is responsible for discarding the relevant packet.

The irx_err signal reflects the following errors:

  • CRC24 errors
  • Loss of lane alignment
  • Illegal control word
  • Illegal framing pattern
  • Missing SOP or EOP indicator

The irx_err output signal is aligned with irx_eopbits, and is always asserted when irx_eopbits has the value of 4'b0001. However, irx_eopbits can have the value of 4'b0001 when irx_err is not asserted, if the error indication arrived on the Interlaken link but the 50G Interlaken IP Core does not detect any of the listed integrity issues in the incoming packet communication.

The irx_err signal indicates approximately where an error occurs: the corruption could have occurred at the SOP of the current packet, in some later cycle in the payload of the current packet, in a packet that is interleaved with the current packet, or in the current EOP cycle. When the IP core identifies an error in the data it receives on the Interlaken link, it marks every packet currently open on the link as errored, rather than attempt to associate the error with a specific channel. Therefore, the application need not drop any packets that are not marked explicitly as errored using one of the two mechanisms.

The irx_err signal asserts one time only, whether a single error or multiple errors occurred in the packet. If the current EOP cycle data is corrupted so badly that the EOP indication is missing, the irx_err error indication is aligned to the next EOP. If an error occurs during an IDLE cycle, the irx_err is aligned to the next EOP.

The application is responsible for discarding packets it receives from the IP core with irx_err asserted during the EOP cycle, just as it is responsible for discarding packets it receives from the IP core with irx_eopbits set to 4'b0001. The application is not responsible for tracking the open packets interleaved with the errored packet — the 50G Interlaken IP Core asserts irx_err in the EOP cycle of every potentially errored packet, and the application can rely on the fact that if irx_err is not asserted and irx_eopbits has a value other than 4'b0001, the packet is not errored.

For CRC24 errors, you should use the crc24_err status signal, rather than relying on the irx_err signal, in the following situations:

  • If you monitor the link when only Idle control words are being received (no data is flowing), you should monitor the real time status signal crc24_err.
  • If you maintain a count of CRC24 errors, you should monitor the number of times that the real time status signal crc24_err is asserted.