50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents

8.1.1. Required User Clock Frequency

The TX_USR_CLK_MHZ parameter specifies the expected frequency of the input clocks tx_usr_clk and rx_usr_clk.

The default value of this parameter is 250 MHz. The range of allowed values is 200 MHz to 300 MHz. You must drive the two input clocks at the frequency specified by this parameter.