50G Interlaken Intel® FPGA IP User Guide

Download PDF
ID 683217
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 50G Interlaken IP Core 3. 50G Interlaken IP Core Parameter Settings 4. Functional Description 5. 50G Interlaken IP core Signals 6. 50G Interlaken IP Core Register Map 7. 50G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 50G Interlaken IP core 10. 50G Interlaken Intel® FPGA IP User Guide Archives 11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide A. Performance and Fmax Requirements for 40G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Raw Aggregate Bandwidth
2. Getting Started With the 50G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 50G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 50G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 50G Interlaken IP Core Parameter Settings x
3.1. Meta Frame Length in Words 3.2. Enable Native PHY Debug Master Endpoint (NPDME) 3.3. Transceiver Reference Clock Frequency 3.4. Number of Calendar Pages 3.5. TX Scrambler Seed 3.6. Transfer Mode Selection
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. 50G Interlaken IP Core Transmit Path 4.6. 50G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 50G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.5. 50G Interlaken IP Core Transmit Path x
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples 4.5.2. 50G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.5.3. 50G Interlaken IP Core Transmit Path Blocks
4.5.1. 50G Interlaken IP Core Transmit User Data Interface Examples x
4.5.1.1. 50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.5.1.2. 50G Interlaken IP Core Packet Mode Operation Example 4.5.1.3. 50G Interlaken IP Core Back-Pressured Packet Transfer Example
4.5.3. 50G Interlaken IP Core Transmit Path Blocks x
4.5.3.1. 50G Interlaken IP Core TX Transmit Buffer 4.5.3.2. 50G Interlaken IP Core TX MAC 4.5.3.3. 50G Interlaken IP Core TX PCS 4.5.3.4. 50G Interlaken IP Core TX PMA
4.6. 50G Interlaken IP Core Receive Path x
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples 4.6.2. 50G Interlaken IP Core RX Errored Packet Handling 4.6.3. In-Band Calendar Bits on the 50G Interlaken IP Core Receiver User Data Interface 4.6.4. 50G Interlaken IP Core Receive Path Blocks
4.6.1. 50G Interlaken IP Core Receive User Data Interface Examples x
4.6.1.1. 50G Interlaken IP Core Receiver Side Example
4.6.2. 50G Interlaken IP Core RX Errored Packet Handling x
4.6.2.1. 50G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.6.4. 50G Interlaken IP Core Receive Path Blocks x
4.6.4.1. 50G Interlaken IP Core RX PMA 4.6.4.2. 50G Interlaken IP Core RX PCS 4.6.4.3. 50G Interlaken IP Core RX MAC 4.6.4.4. 50G Interlaken IP Core RX Regroup Block
5. 50G Interlaken IP core Signals x
5.1. 50G Interlaken IP Core Clock Interface Signals 5.2. 50G Interlaken IP Core Reset Interface Signals 5.3. 50G Interlaken IP Core User Data Transfer Interface Signals 5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 50G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 50G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Required User Clock Frequency 8.1.2. Counter Reset Bits 8.1.3. Include Temp Sense 8.1.4. RXFIFO Address Width 8.1.5. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) 8.1.6. Use ATX or CMU PLL 8.1.7. Lane Profile
9. Out-of-Band Flow Control in the 50G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic

2.6.2. Transceiver Logical Channel Numbering

In Arria V and Stratix V devices, logical channel numbering starts from zero. The logical channel numbering starts at the bottom of the die with logical channel 0 and continues in physical pin order through the four ordered transceiver blocks on the same side of the device. Each data channel and TX PLL has its own dedicated reconfiguration interface with an assigned logical channel.

In Intel® Arria® 10 devices, you control the mapping of Interlaken lanes directly in the Intel® Arria® 10 Native PHY IP core that is included in the 50G Interlaken IP core.

In Arria V and Stratix V devices, you can control the logical channel assignments in the IP core. You typically assign lanes to match the logical channel numbering. However, the default Interlaken lane assignment does not assign a lane to Channel 1 or Channel 4 in a transceiver block, leaving either available for the CMU PLL. You can use the information in the following table to map the lanes to their default logical channel numbering. The logical channel numbering always starts at the bottom of a transceiver block.

Table 8.  Transceiver Logical Channel NumberingThe default expected mapping of logical channels to Interlaken lanes in Arria V and Stratix V devices.

Transceiver Block Number

Logical Channel Number in Device

Direction

Interlaken Lane Number in IP Core

27

TX PLL 3

3

26

TX

RX

25

TX

RX

24

TX

RX

23

TX

RX

22

TX

RX

21

TX

RX

20

TX PLL 2

2

19

TX

RX

18

TX

RX

17

TX

RX

16

TX

RX

15

TX

RX

14

TX

RX

13

TX PLL 1

1

12

TX

7

RX

11

TX

(Left available for CMU PLL)

RX

10

TX

6

RX

9

TX

5

RX

8

TX

(Left available for CMU PLL)

RX

7

TX

4

RX

6

TX PLL 0

0

5

TX

3

RX

4

TX

(Left available for CMU PLL)

RX

3

TX

2

RX

2

TX

1

RX

1

TX

(Left available for CMU PLL)

RX

0

TX

0

RX

For example, in an Arria V or Stratix V device, to change the VOD setting for lane 7, you write logical channel  12 to the Reconfiguration Controller.

Related Information
Level Two Title