50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Document Table of Contents 50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example

In Interleaved Mode, you are responsible for scheduling the burst. You need to drive an extra pair of signals, Start of Burst (SOB) and End of Burst (EOB), to indicate the burst boundary. You can send the traffic in packet order or interleaved order, as long as you set the SOB and EOB flags correctly to establish the data boundaries.

Figure 11. Packet Transfer on Transmit Interface in Interleaved Mode

This example illustrates the expected behavior of the 50G Interlaken IP core application interface transmit signals during data transfers from the application to the IP core on the TX user data transfer interface in interleaved mode.

The figure shows the timing diagram for an interleaved data transfer in Interleaved mode. In cycle 1, the application asserts itx_sop and itx_sob , indicating that this cycle is both the start of the burst and the start of the packet. The value the application drives on itx_chan indicates the data originates from channel 2.

In cycle 2, the application asserts itx_eob, indicating the data the application transfers to the IP core in this clock cycle is the end of the burst. (itx_chan only needs to be valid when itx_sob or itx_sop is asserted). itx_num_valid[2:0] indicates all four words are valid. However, the data in this cycle is not end of packet data. The application is expected to transfer at least one additional data burst in this packet, possibly interleaved with one or more bursts in packets from different data channels.

Cycle 3 is a short burst with both itx_sob and itx_eob asserted. The application drives the value of three on itx_num_valid[2:0] to indicate that three words of the four-word itx_din_words data bus are valid. The data is packed in the most significant words of itx_din_words.The application drives the value of 4'b1011 on itx_eopbits to indicate that the data the application transfers to the IP core in this cycle are the final words of the packet, and that in the final word of the packet, only three bytes are valid data. The value the application drives on itx_chan indicates this burst originates from channel 4.

In cycle 4, the itx_num_valid[2:0] signal has the value of zero, which means this cycle is an idle cycle.

In cycle 5, the application sends another single-cycle data burst from channel 2, by asserting itx_sob and itx_eob to indicate this data is both the start and end of the burst. The application does not assert itx_sop , because this burst is not start of packet data. itx_eopbits has the value of 4'b0000, indicating this burst is also not end of packet data. This data follows the data burst transfered in cycles 1 and 2, within the same packet from channel 2.

In cycle 6, the application sends a start of packet, single-cycle data burst from channel 3.

In cycles 7 and 8, the application sends a two-cycle data packet in one two-cycle burst. In cycle 8, the second data cycle, the application drives the value of two on itx_num_valid[2:0] and the value of 4'b1011 on itx_eopbits, to tell the IP core that in this clock cycle, the two most significant words of the data symbol contain valid data and the remaining words do not contain valid data, and that in the second of these two words, only the three most significant bytes contain valid data.

In Interleaved Mode, you can transfer a packet without interleaving as long as the channel number does not toggle during the same packet transfer. However, you must still assert the itx_sob and itx_eob signals correctly to maintain the proper burst boundaries.

If you do not drive the itx_sob and itx_eob signals, the 50G Interlaken IP Core does not operate properly and the transmit FIFO may overflow, since in this mode the internal logic is looking for itx_sob and itx_eob assertion for insertion of proper burst control words.

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