1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 50G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 50G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
5.1. 50G Interlaken IP Core Clock Interface Signals
5.2. 50G Interlaken IP Core Reset Interface Signals
5.3. 50G Interlaken IP Core User Data Transfer Interface Signals
5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 50G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
3.3. Transceiver Reference Clock Frequency
The Transceiver reference clock frequency parameter specifies the expected frequency of the pll_ref_clk input clock.
If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this parameter, the design fails in both simulation and hardware.
The 50G Interlaken IP core supports the following pll_ref_clk frequencies: 156.25 MHz, 195.3125 MHz, 250 MHz, 312.5 MHz, 390.625 MHz, 500 MHz, and 625 MHz.
The default value of the Transceiver reference clock frequency parameter is 312.5 MHz.
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