50G Interlaken Intel® FPGA IP User Guide

ID 683217
Date 10/31/2022
Public
Document Table of Contents

3.2. Enable Native PHY Debug Master Endpoint (NPDME)

The Enable Native PHY Debug Master Endpoint (NPDME) parameter specifies whether your Intel® Arria® 10 50G Interlaken IP core variation supports the ADME feature.

This parameter exposes debugging features of the Intel® Arria® 10 Native PHY IP core that specifies the transceiver settings in the 50G Interlaken IP core. You can turn this parameter on to enable the following Intel® Arria® 10 Native PHY IP core features:

  • Enable Native PHY Debug Master Endpoint (NPDME)
  • Enable capability registers
  • Enable prbs soft accumulators
  • Enable odi acceleration logic

A checkmark in the check box to the left of the parameter turns this parameter on. When the parameter is turned on, the IP core include these transceiver reconfiguration capabilities. A check box with no checkmark indicates that the option is turned off, and the IP core does not support these features.

By default, the Enable Native PHY Debug Master Endpoint (NPDME) parameter is turned off.

This parameter is available only for 50G Interlaken IP core variations that target an Intel® Arria® 10 device.